Low power fast fourier transform and combiner of multi carrier-code division multiple access receiver system for wireless sensor networks

This thesis presents a low power fast Fourier transforms (FFT) and combiner of multi-carrier code division multiple access (MC-CDMA) receiver for wireless sensor networks (WSN). WSN is a system comprises of sensor nodes with data sampling, data processing, and communication capabilities. In WSN, there is the need for scheduling of various communication activities between sensor nodes to the cluster-head or the neighbouring nodes. Most of the WSN adapt the time division multiple access (TDMA) and media access control (MAC) layer approach techniques for scheduling purposes. The main question was how to ensure the channel is most productive when the sensor nodes have the urge to transmit the data available but cannot because of the scheduling protocol adapted by the WSN. Besides, scheduling contributes to higher power consumption for sensor nodes in WSN, reducing the sensor nodes lifetime. This research is motivated by the desire to eliminate scheduling in the WSN communication protocol with low power MC-CDMA system designs. MC-CDMA offers a collision-free medium since MC-CDMA can process transmit or receive data simultaneously over a single communication channel. Most of the sensor nodes are battery operated and sometimes placed in an isolated area, making it difficult to change the battery or connect to a direct power supply. Thus, the design must be in low power for longer lifespan of the nodes. In this research, different point (16, 64, and 256-point) and radixes (radix-4 and radix-8) FFT module, and combiner module are considered and analysed. Integration of both modules forms the MC-CDMA receiver. Pipelined FFT function is to convert signal in the time domain to the frequency domain, while combiner performs despreading, channel estimation and data demodulation to recover the transmitted bits. The low power designs in MC-CDMA have been carried out using Verilog coding in Modelsim software, and the design verifications are done through Matlab. The design implementation is via Quartus and programmed on DE2-115 Altera field-programmable gate array (FPGA) board. Synopsys is used for power and area consumption studies with 90nm CMOS Technology. The functionality analyses have been carried out on simulation, and the hardware implementation of the MC-CDMA receiver is tested to see the MC-CDMA receiver ability to received data without scheduling. Both simulation and hardware execution are successful where the receiver received and displayed the output accordingly. MC-CDMA achieves 39.13mW power consumption and 0.95mm2 design area consumption. Signal-to-noise (SNR) module was implemented on the receiver, and the results show that average SNR for MC-CDMA receiver is above 31.92dB, good SNR result for wireless communication. The optimization process by removing all hierarchical design has reduced the power and area consumption with 59.61% power saving and 30.07% area saving. MC-CDMA implementation on FPGA board gave a total of 28.57mW power consumption and used 2,072/114,480 logic elements which are 2% of overall logic elements. In conclusion, MC-CDMA receiver design in this thesis is small, low in power, have good SNR value and the ability to eliminate scheduling, which is suitable for WSN sensor nodes processor.

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