Citation
Zakaria, Nor Azura
(2013)
Multiple and solid data background scheme for testing static single cell faults on SRAM memories.
Masters thesis, Universiti Putra Malaysia.
Abstract
Memory testing is a method that requires an algorithm capable of detecting faulty
memory as comprehensively as possible to facilitate the efficient manufacture of fault
free memory products. Therefore, the purpose of this thesis is to introduce a Data
Background (DB) scheme to generate an optimal March Test Algorithm (MTA) for
detecting faults of memory that are undetectable using existing algorithms. The
present research focuses on two types of Static Single Cell Faults (SSCFs): Write
Disturb Faults (WDFs) and Deceptive Read Destructive Faults (DRDFs). These faults
are undetectable by existing algorithms with insufficient operation. To date, the main
effort in this field of research is to improve fault detection by modifying or adding an
operation sequence in the MTA. A relatively small number of test approaches have
worked on the DB scheme instead of the MTA to improve fault coverage. However,
these approaches were designed to improve the fault coverage for detectable faults
only. Thus, the present research develops a new DB scheme to be applied to existing
MTA to detect two WDFs and two DRDFs.
Two methods are proposed in this project. In Method 1, a multiple DBs generator with
a bit-adjacent DB management scheme is applied for the selected MTA. This method
is evaluated in terms of function and performance differences between the proposed
MTA and existing MTA using the User Defined Algorithm (UDA) available in the
MBISTArchitect tool. Findings show that both MTAs have the same testing time.
However, the existing MTA of the Memory Built-In-Self Test (MBIST) required a
bigger area overhead and consumed more power. Hence, Method 1 is not suitable to
be used with the MBIST for System on Chip (SoC). For Method 2, suitable solid DBs are used to provide higher fault coverage instead of
using the existing MTA. The new MTA is defined by designing an automation
program called DB generator. The DB generator computes all the possible DBs and
filters the list of preferable DBs using efficient combination logic. The proposed MTA
is obtained after the eliminating procedure of the preferable DB list using the SQ
generation rule. Finally, the fault coverage will be calculated manually by doing fault
evaluation analysis using Fault Primitives (FP) rules. Results show that WDFs and
DRDFs are successfully detected with each proposed MTA. The proposed MTAs are
also able to detect other SSCFs, such as Transition Fault, Stuck-At Fault, Incorrect
Read Fault, Read Destructive Fault, and State Fault. Finally, based on the SQ
generation rule, and the development of the DB generator, MTAs are generated. The
present research demonstrates that the DB generator and proposed MTAs, such as
March CL-1, March Cl-2, March SR-1, and March SR-2, are successfully applied and
designed, with up to 100% fault coverage.
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Additional Metadata
Item Type: |
Thesis
(Masters)
|
Subject: |
Metal oxide semiconductors, Complementary |
Subject: |
Computer storage devices - Design and construction |
Call Number: |
FK 2013 142 |
Chairman Supervisor: |
Associate Professor Wan Zuha Wan Hasan, PhD |
Divisions: |
Faculty of Engineering |
Depositing User: |
Ms. Nur Faseha Mohd Kadim
|
Date Deposited: |
16 Nov 2020 05:57 |
Last Modified: |
04 Jan 2022 03:09 |
URI: |
http://psasir.upm.edu.my/id/eprint/84183 |
Statistic Details: |
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