FPGA implementation of handwritten number recognition using artificial neural network

Citation

Mittal, Harsh and Sharma, Abhishek and Perumal, Thinagaran (2019) FPGA implementation of handwritten number recognition using artificial neural network. In: 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE), 15-18 Oct. 2019, Osaka, Japan. (pp. 1010-1011).

Abstract

Implementation of Deep Learning and Machine Learning Algorithms is always a challenge as they consume a lot of resources and power. In this paper, we have presented a very simple yet efficient way for creating an IP (intellectual property) core for Handwritten Number Recognition for FPGAs. The proposed ANN was verified and compared with several ANN networks on MATLAB, which gave the accuracy of about 99.38%. This network was implemented on Xilinx Zybo board XC7Z010CLG400-1. The total area covered by the IP block is 27.9%. The IP created is efficient and uses fewer resources thus suitable for other embedded applications.

Download File

Text (Abstract)
FPGA implementation of handwritten number recognition using artificial neural network.pdf
Download (4kB)

Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Computer Science and Information Technology
DOI Number:	https://doi.org/10.1109/GCCE46687.2019.9015236
Publisher:	IEEE
Keywords:	FPGA; Handwritten number recognition; Artificial neural network
Depositing User:	Nabilah Mustapa
Date Deposited:	02 Jun 2020 03:10
Last Modified:	02 Jun 2020 03:10
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/GCCE46687.2019.9015236
URI:	http://psasir.upm.edu.my/id/eprint/78077
Statistic Details:	View Download Statistic

Actions (login required)

View Item