A complexity-reduced digital predistortion for radio frequency power amplifier

Power amplifier (PA) is a major source of nonlinearity in a communication system since it often has to operate close to the saturation region to achieve high power efficiency. The nonlinearity includes out-of-band emission which causes adjacent channel interference and in-band distortion that degrades the bit error rate performance. In modern high speed communications, transmission schemes with high spectral efficiency such as Code Division Multiple Access (CDMA) and Orthogonal Frequency Division Multiplexing(OFDM) are more sensitive to PA nonlinearity and memory effects. In order to overcome the conflict between the linearity and the power efficiency of the PA, a linearization technique is required. One of the most cost-effective linearization techniques is Digital Pre-Distortion (DPD). The main justification for a DPD is to improve PA efficiency since PA is the most power consuming device in a transmitter. However, high complexity DPD leads to high power consumption due to intensive processing. Therefore, it is essential that the power saved by using DPD is not spent on a high complexity DPD algorithm.In this thesis, a low-complexity DPD model is proposed, verified, and experimentally evaluated for linearizing power amplifiers with memory effects. The proposed model derived from Volterra-series includes three parallel dynamic branches. This proposed model is constructed by treating the linear and nonlinear memory effects separately,which will provide an effective way to present efficient distortion compensation with lowcomplexity for PA linearization. The performance of the proposed model is assessed using a commercial class-AB power amplifier driven by a 2-carrier Wideband CDMA(WCDMA) signal of 15 MHz bandwidth and Long-Term Evolution (LTE) signals of 15 MHz and 20 MHz bandwidth. The simulation and experimental results show that the proposed model outperforms the MP model in terms of Adjacent Channel Leakage power Ratio (ACLR) performance by 7 dB and 6 dB, respectively for the 15 MHz bandwidth and by 6.8 dB and 6.5 dB, respectively for the 20 MHz bandwidth. These results were achieved with a reduction in the complexity by 16% in terms of number of floating point operations (FLOPs) as compared to the MP’s model complexity. This work demonstrates that a high linearity performance was achieved while the computational complexity of the proposed DPD model was minimized. These improvements will lead to reduction in transmitter power consumption and also reduction in hardware resources required for onchip DPD implementation.

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