Design of a wide-range CMOS digital delay line with sub-picosecond jitter for image sensor applications

Development of high-performance CMOS delay lines is becoming a crucial necessity for many advanced applications such as high-speed computer memory controllers and advanced time-resolved image sensors such as Time-of-Flight (ToF)image sensors and Fluorescence Lifetime Imaging Microscopy (FLIM) image sensors that would benefit from having a high-performance delay line integrated along with the system as a SoC solution. In this thesis, a 3-stage architecture CMOS digital delay line is proposed, designed, and analysed for generating picosecondresolution delay steps, microsecond delay range, and at a sub-picosecond jitter performance.To achieve wide delay range with fine-linear delay steps, a 3-stage circuit is proposed. In the first stage, a new 10-bit counter-based circuit is developed to allow a delay range of up to 2s in steps of 2ns. The coarse delay output of this stage is fed to a medium-resolution second stage. The second stage uses a typical tapped-delay line topology that exploits the propagation delay of stacked logic circuits to generate medium-resolution delay steps. This stage generates a delay range of 2ns with steps of 65ps. This stage is used to interpolate between the coarse-resolution delay steps generated in the first stage. The output of this stage is then fed to a third stage designed using a Delay-Locked Loop (DLL) circuit with a new charge resetting technique. The charge pump of the DLL is reset by a specialized circuit designed to trigger using the input signal that is to be delayed. A small-signal model of the proposed circuit along with analytical modeling are presented to show the relationship between the DLL's internal control voltage and output fine time delay steps. The delay range generated for this last and third stage is 70ps with a step of 1ps. This fine delay stage is used to interpolate between the medium-resolution delay steps generated in the second stage. The output of the entire delay line is read at the output of this final stage.The delay specifications for the 3-stage CMOS digital delay line in this work are confirmed by simulation using a standard 0.13μm Silterra CMOS process. Apart from the mentioned delay specifications, analyses show that the Integral-Non Linearity (INL) of the first stage, second stage, and third stage is 0.13LSB, 1.94LSB,and 1.7LSB, respectively. The jitter performance at the output of the third stage is only 0.39ps RMS. The total power consumption of the full implemented 3-stage CMOS digital delay line circuit is only 2.7 μW. The active layout area of this delay line is approximately (285220) μm2 making it suitable to be integrated as a SoC solution for chips that may require high-delay specifications.

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