Implementation of multi-class shared buffer with finite memory size

Citation

Abdul Rahman, Abdul Aziz and Seman, Kamaruzzaman and Saadan, Kamarudin and Azman, Azreen (2011) Implementation of multi-class shared buffer with finite memory size. In: 17th Asia-Pacific Conference on Communications (APCC 2011), 2-5 Oct. 2011, Sutera Harbour Resort, Kota Kinabalu, Sabah, Malaysia. (pp. 548-552).

Abstract

High packet network have become an essential in modern multimedia communication. Shared buffer is commonly used to utilize the buffer in the switch. In this paper, we analyse the performance of shared buffer with different memory sizes. The architecture of the multi-class shared buffer is developed for 16×16 ports switch that is targeted in Xilinx FPGA. The performance of the multi-class shared buffer switch is analysed in term of throughput and mean delay. Based on the simulation with different memory sizes, it is observed that the optimum selection of memory size under uniform traffic depends on the maximum traffic load of the switch.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Computer Science and Information Technology
DOI Number:	https://doi.org/10.1109/APCC.2011.6152869
Publisher:	IEEE
Keywords:	Shared buffer; Multi-class; Finite memory size; Architecture design; FPGA
Depositing User:	Nabilah Mustapa
Date Deposited:	08 Jul 2019 02:43
Last Modified:	08 Jul 2019 02:43
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/APCC.2011.6152869
URI:	http://psasir.upm.edu.my/id/eprint/69630
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