Design Of 1K Asynchronous Static Random Access Memory Using 0.35 Micron Complementary Metal Oxide Semiconductor Technology

Static Random Access Memory (SRAM) is a high speed semiconductor memory which is widely used as cache memory in microprocessors and microcontrollers, telecommunication and networking devices. The SRAM operations are categorized into two main groups: asynchronous and synchronous. A synchronous SRAM has external clock input signal to control all the memory operation synchronously at either positive or negative edge of the clock signal. While, in asynchronous SRAM, the memory events are not referred or controlled by the external clock. In this study, we have proposed an asynchronous SRAM which configured with a self-holding system in the control unit. The self-holding SRAM control system can produce appropriate signals internally to operate the SRAM system automatically, eliminating hold and wait time, and eliminating Sense Enable and Output Enable signals which usually used in SRAM control system. All input signals are synchronized by the internal control unit. The overall SRAM operations however do not depend on the rising of falling edge of the global (external) clock signal, and thus, the design is still categorized under asynchronous SRAM. The proposed self-holding control system has been developed for a 1 kilobit SRAM using MIMOS 0.35 micron 3.3V CMOS technology Due to limited computer resources such as speed and space, the design had been limited to 1 kilobit memory size. The design covers both schematic and layout designs using Hspice and Cadence Layout Editor, respectively. Meanwhile analysis covers Hspice, Timernill and LVS (Layout versus Schematic). The simulation results have shown the self-holding SRAM control system was working successfully. The design operation speed was 7.0% faster as compared to the SRAM system without the self-holding circuit. An operation speed of 66Mhz with access time of 2.85ns was achieved.

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