New tool for converting high-level representations of finite state machines to verilog HDL

Citation

Masoumidezfouli, Seyedhossein and Syed Mohamed, Syed Abdul Rahman Al-Haddad and Rokhani, Fakhrul Zaman (2017) New tool for converting high-level representations of finite state machines to verilog HDL. In: 2017 IEEE 15th Student Conference on Research and Development (SCOReD), 13-14 Dec. 2017, Putrajaya, Malaysia. (pp. 1-6).

Abstract

Automated conversion of high-level representation of Finite State Machine (FSM) to correct-by-construction Hardware Description Language (HDL) is of demand with the increasing complexity of the modern digital controller designs. In this paper, we proposed a tool implementing systematic methodology for conversion and verification of high-level FSM to Verilog HDL. User defined options are provided to increase the flexibility and usability of the tool. MCNC91 benchmarks were used to evaluate the tool performance and correctness. Results indicate that the tool is able to correctly convert all given benchmark circuits with good runtime and memory consumption.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/SCORED.2017.8305431
Publisher:	IEEE
Keywords:	Finite state machine; Automation; EDA tool; Conversion
Depositing User:	Nabilah Mustapa
Date Deposited:	06 Mar 2018 02:33
Last Modified:	06 Mar 2018 02:33
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/SCORED.2017.8305431
URI:	http://psasir.upm.edu.my/id/eprint/59460
Statistic Details:	View Download Statistic

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