Sub-picosecond jitter resolution wide range digital delay line for SoC integration

Citation

Abdulrazzaq, Bilal Isam and Abdul Halin, Izhal and Mohd Sidek, Roslina and Shafie, Suhaidi and Md Yunus, Nurul Amziah and Kawahito, Shoji (2015) Sub-picosecond jitter resolution wide range digital delay line for SoC integration. In: 2015 IEEE International Circuits and Systems Symposium (ICSyS 2015), 2-4 Sept. 2015, Holiday Villa Beach Resort & Spa, Langkawi, Kedah. (pp. 44-48).

Abstract

A novel three-stage architecture programmable digital delay line (DDL) with a picosecond resolution, 1μs range, and sub-picosecond jitter performance is proposed. Through circuit simulation, a dynamic range of 1μs is obtained in the first stage using 10-bit counters operating at a frequency of 1 GHz. The second stage further refines the delay to 23ps using a tapped inverter chain architecture. Finally, the third stage constructed using a DLL with NAND gate based delay elements further refines the delay step to 1ps resolution with a 0.1ps RMS jitter performance. The proposed digital delay line is designed using a standard 0.13μm Silterra CMOS technology.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/CircuitsAndSystems.2015.7394062
Publisher:	IEEE
Keywords:	Delay element; Delay step; Delay-locked loop (DLL); Digital delay line; Dynamic range; Inverter; Jitter; SoC
Depositing User:	Nabilah Mustapa
Date Deposited:	03 Jul 2017 09:25
Last Modified:	03 Jul 2017 09:25
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/CircuitsAndSystems.2015.7394062
URI:	http://psasir.upm.edu.my/id/eprint/55971
Statistic Details:	View Download Statistic

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