Hardware Implementation Of Rc4a Stream Cipher Algorithm

The security of sensitive information against ‘prying eyes’ has been of prime concern throughout the centuries. Therefore, a mechanism is required to guarantee the security and privacy of information. Under the existing circumstances cryptography is the only convenient method for protecting information transmitted through communication networks. The hardware implementation of cryptographic algorithms plays an important role because of growing requirements of high speed and high level secure communications. Accordingly, in this research attempt is taken to develop a faster and reliable cryptographic hardware by implementing one of the stream ciphers, RC4A in hardware. Verilog Hardware Description Language (HDL) and top down design methodology has been used to design the hardware implemented in this thesis. For hardware implementation of the design, an Altera Field Programmable Gate Array (FPGA) device, EP20K200EFC484-2X from APEX family, APEX 20KE, has been used. The designed hardware consumed 480 logic elements, 146 I/Os, and 10,240 bits memory. The hardware implementation achieved the data transfer rate of 22.28 MB/S in a clock frequency of 33.33 MHz. The implementation is able to support variable key lengths from 8 bits up to 512 bits. Unlike other stream ciphers, the proposed implementation generates two output streams at a time, whereas others generate only one output stream. So, user may use any of keystream which increase the unpredictability of the key as well as security.

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