Design of a reconfigurable FFT processor using multi-objective genetic algorithm

Citation

Pang, Jia Hong and Sulaiman, Nasri (2010) Design of a reconfigurable FFT processor using multi-objective genetic algorithm. In: International Conference on Intelligent and Advanced Systems (ICIAS 2010), 15-17 June 2010, Kuala Lumpur, Malaysia. .

Abstract

This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make sure the processor operates at acceptable Signal to Noise Ratio (SNR). Reducing the wordlength of FFT coefficient will contribute to lower Switching Activity (SA), thus lower power consumption is required for the operation of FFT processor.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/ICIAS.2010.5716157
Publisher:	IEEE
Keywords:	FFT processor; Signal to noise ratio; Switching activity
Depositing User:	Nabilah Mustapa
Date Deposited:	15 Jul 2016 05:24
Last Modified:	15 Jul 2016 05:24
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/ICIAS.2010.5716157
URI:	http://psasir.upm.edu.my/id/eprint/47776
Statistic Details:	View Download Statistic

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