Dual-sampling sigma-delta analog-to-digital converter implementation in field-programmable gate array

With the latest advancement in field-programmable gate array (FPGA) technology,the analog-to-digital converter (ADC) can now be integrated within the FPGA digital fabric without the need for an external ADC chip. Realization of the ADC is possible by utilizing the low voltage differential signaling (LVDS) pin pair available on the FPGA chip along with some external passive components. The implementation of ADC in the FPGA chip has a few advantageous where the cost, board space and components are reduced. The FPGA no longer needs an external ADC to be integrated with the analog interfaces. FPGA implementation of ADC structures such as successive approximation register (SAR) and sigma-delta ADC are considered and their performances are evaluated. In a close loop digital controller application such as motor controller, it requires a fast ADC conversion to drive a motor with a quick feedback response. SAR ADC is capable of fast conversion time while the sigma-delta ADC sacrifices a fast conversion time for accuracy. However, the SAR ADC conversion contains errors in FPGA implementation and sigma-delta ADC is too slow for a practical close loop system. A dual-sampling sigma-delta (DSSD) ADC is proposed utilizing the potential of the sigma-delta ADC and maximizing the usage of FPGA. The proposed ADC is capable of sampling both clock edges instead of the conventional single edge sampling. The sampled analog signal is feedback through an RC filter network which will be tracked and compared with the analog input signal. The result for each clock edges are summed to obtain the final converted digital word. Thus, the workload is distributed since the sampling data is divided into two clock edges. It allows faster data processing and maximizing data throughput. The aim of this research is to reduce the ADC conversion time while maintaining the quality of the signal converted. The performance of the DSSD ADC is compared with other ADC structures implemented in FPGA. The performance of the proposed ADC structure is written in verilog hardware description language (HDL) and evaluated using the Altera Cyclone II FPGA chip on a Development and Education (DE) II board. The results show the proposed 8-bit DSSD ADC with 27 MHz sampling clock provides the ADC with 1 least significant bit (LSB) error, 4.8 μs conversion time and a bandwidth of 104.1 kHz. The DSSD ADC structure has improved from the conventional sigma-delta structure which is 3 LSBs, 9.4 μs conversion time and bandwidth of 53.2 kHz.

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