Design of segmented 14-bit low power current steering digital to analog converter

Digital to Analog Converter (DAC) function is to convert a given string of digital input into an analog voltage or current value. Due to its functionality, DACs is considered an essential system used to interface between digital and analog systems. The past few decades have seen many methods of realizing DAC circuits such as the resistive ladder networks, binary-weighted structure, pulse-width modulators, thermometer-coded architecture and hybrid structures. These implementations have yielded high resolution and high performance DACs that find application generally in consumer electronics, automotive industry and even in the medical field. For example video signal processing and wireless communications apply DACs capable of handling data at speeds of several hundreds of mega samples per second with a resolution of 12 to 14 bits. According to literature, majority of the advanced DACs used in these devices concentrate on low power architectures. To achieve low power, they utilize currentsteering circuits consisting of either the binary-weighted structure, thermometercoded (unary) architecture or by taking the advantage of both methods in a segmented DAC architecture. For any given digital input code, the current steering circuits are responsible for generating the analog output value and are also responsible for static power dissipation. However, available DACs do not focus on reducing the static power dissipation. Moreover, static power dissipation will rise as future applications must demand for higher resolution DACs which translate to an increase in current sources that dissipate even more static power. This work proposes a method to address the static power dissipation of a ighresolution 14-bit DAC. The DAC consists of a digital module and an analog module. The analog module consists of switched current sources and arrays of current cells which contribute much to static power dissipation. To allow for low static power dissipation, unselected current sources are put in hibernation mode. In this mode the cells operate at half of their nominal currents. Towards this end, the transistors in the current sources still operate in the saturation region but at half their nominal current which translates to a reduction in static power dissipation. On the other hand, the digital module is designed using latch circuits, thermometer decoder circuits and latency equalizer circuits. This work also highlights the novel design and simulation of the latency equalizer circuit that is used to synchronize different segments of the DAC during its operation. This circuit introduces delays to currents generated from the many current cells in order for them to arrive simultaneously at the current summing node. The design is optimized in order for the DAC to operate at a speed of 100MHz. As a proof of concept, the TSMC 0.18μm technology is used to design and simulate the DAC. It is shown that a 50% reduction of current in hibernation mode which is from 256 μA to 128μA, allows the total power dissipation of the DAC to be 25mW at an operation speed of 100MHz. Functionality simulation reveal that the designed DAC has an INL and DNL of less than 0.5 LSB, respectively. When compared to specifications of similar DACs in literature, the total power consumption of this DAC which is approximately 25mW exhibits approximately 69% improved power dissipation.

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