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Analysis and modeling of ASIC area at early-stage design for standard cell library selection


Citation

Lim, Yang Wei and Hashim, Shaiful Jahari and Kamsani, Noor 'Ain and Mohd Sidek, Roslina and Rokhani, Fakhrul Zaman (2019) Analysis and modeling of ASIC area at early-stage design for standard cell library selection. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 26-29 May 2019, Sapporo, Japan. .

Abstract

Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optimal library for designing area-optimized circuit. The model predicts the area-delay curves for a target circuit based on reduced number of synthesis performed at different frequencies. As compared to the general linear search method, the proposed model with 5 synthesis points results 16.5X-18.6X runtime reduction with average error of 2.74%~5.74% in different height libraries implementation. This shows that the proposed model is beneficial for area optimal library selection at the early stage of design.


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Additional Metadata

Item Type: Conference or Workshop Item (Paper)
Divisions: Faculty of Engineering
DOI Number: https://doi.org/10.1109/ISCAS.2019.8702691
Publisher: IEEE
Keywords: Area estimation; Analysis and modeling; ASIC design; Logic synthesis; Standard cell; Cell height
Depositing User: Nabilah Mustapa
Date Deposited: 15 Jun 2020 07:48
Last Modified: 15 Jun 2020 07:48
Altmetrics: http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/ISCAS.2019.8702691
URI: http://psasir.upm.edu.my/id/eprint/36345
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