Fabrication and simulation of P-type junctionless silicon nanowire transistor using silicon on insulator and atomic force microscope nano lithography

Departing from microelectronic to nanoelectronics, nowadays, is one of the promising and crucial areas in the field of nanotechnology. Relevant difficulties emerge from this scaling down electronic device to nanometres dimension are the fabricating process of nanostructures and understanding the transport mechanism. Scanning tunneling microscope (STM) and atomic force microscope (AFM) commonly used for measuring surface properties of materials at atomic precision, could be manipulated to fabricating nanoscale electronic devices. In this work, AFM nanolithography via local anodic oxidation (LAO) process was used to fabricate side gate Junctionless Silicon Nanowire Transistors (JLSNWTs). Single element of lightly doped (1015cm-3) p-type (100) silicon-on-insulator (SOI) wafer was used to construct the new JLSNWT consisting common transistor components, the source, the drain, and the gate. The novelty for this device is the nanowire, a channel connecting the source and the drain in a single piece without an ohmic contact. Using AFM nanolithography method the nanowire of length 200 nm, width 100 nm, and thickness 90 nm has successfully constructed. To fabricate JLSNWT, a SOI wafer was cut into a chip of 1 cm x 1 cm size, before undergoing cleaning process to remove ionic, heavy metallic or organic contamination desorption. Hydrogen fluoride in 2% water was treated to the wafer surface for 1 minute to replace the Si–O bonds by low energy Si–H bonds and unreceptive the top Si layer to avoid contaminant and native oxide. The lithographic area on SOI for the construction of JLSNWT was about 15 μm x 15 μm and the fabrication process was observed throughout using an optical microscope with the magnification of 100X attached to CCD camera monitor. The anodization of the Si–H surface was performed under negatively biased to the AFM conductive Cr/Pt tip to draw pre-designed nanoscale oxide pattern of the transistor structure. The lithographic area was chemically etching with diluted KOH and isopropanol to remove Si layer outside the pattern and later with diluted hydrogen fluoride to remove oxide (SiO2) on the pattern and finally leaving p-type Si layer on the pattern of JLSNWT. Two JLSNWTs were fabricated and investigated the performance, each having the gap of 75 and 100 nm respectively, between the gate and the channel.

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