Area efficient test circuit for library standard cell qualification

Citation

Al-Frajat, Jaafar Khadair Kadam and Flayyih, Wameedh Nazar and Mohd Sidek, Roslina and Samsudin, Khairulmizam and Rokhani, Fakhrul Zaman (2015) Area efficient test circuit for library standard cell qualification. In: 5th International Conference on Energy Aware Computing Systems & Applications (ICEAC 2015), 24-26 Mar. 2015, Cairo, Egypt. .

Abstract

High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/ICEAC.2015.7352210
Publisher:	IEEE
Keywords:	Delay chain; Library validation; On-silicon measurement; Standard cell qualification; TEG circuit
Depositing User:	Nabilah Mustapa
Date Deposited:	18 Nov 2009 06:54
Last Modified:	15 Jan 2018 09:08
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/ICEAC.2015.7352210
URI:	http://psasir.upm.edu.my/id/eprint/2848
Statistic Details:	View Download Statistic

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