Design Of Direct Sequence Code Division Multiple Access (Ds-Cdma) Wireless Transmitter Using Field Programmable Gate Array (Fpga)

This thesis describes the DS-CDMA wireless transmitter design using FPGA (Field Programmable Gate Array), which has been adopted in many wireless access technologies. Four separate blocks have been designed using digital approach to form the transmitter circuit diagram using the oscillator, the PN-code generator, the Parity Check, and the BPSK modulator. The Synopsys software has been used for the design synthesis and simulation; the VHDL (Very High Speed Integrated Circuit Hardware Description Language (VHDL» program was used for coding and FPGA for compiling and downloading the simulation in FPGA cards. The DS-CDMA wireless transmitter was designed to transmit with data rates up to 2 Mbps. The transmitted signals were carried out with a 40 MHz carrier frequency. VHDL files were created for each element of the wireless transmitter. Each file was simulated and synthesized using FPGA compiler II. The control block was added for timing purposes and for framing the coded data. One bit parity was added to the data frame containing 1 6 serial bits.The top-level design file was initiated using VHDL for the combined elements of the DS-CDMA wireless transmitter including the control block. The results of simulated and synthesized top-level design file using FPGA compiler II were downloaded into the Xilinx XSV300 FPGA board. This study has demonstrated the design of DS-CDMA wireless transmitter with higher data rates using FPGA. It has also improved the performance and quality of the transmitted data by including error detection and correction.

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