Double adjacent error correction codes for ultra-fast cache memories

Error correction codes are commonly used to protect cache memories from soft errors. As technology feature size scales deeper into sub-nanometer regime, radiation-induced soft error can causes double adjacent error (DAE). Several double adjacent error correction (DAEC) codes have been introduced to address DAEs, however, they miscorrect some nonadjacent double errors. In progress, a class of DAEC orthogonal Latin squares (OLS) codes is introduced to eliminates all miscorrections, using the orthogonality property of OLS codes, and also reduces the decoding delay time. The main drawback comes from the large number of check bits, imposed by the conventional OLS codes. In this paper, two coding approaches are developed based on a modified SEC OLS coding scheme that requires less number of check bits. The first approach is a class of SEC-DED-DAEC codes proposed to reduce the number of check bits compared to the existing SEC-DED-DAEC OLS codes. The second approach is a class of SEC-DAEC codes with a very high speed decoding process. This approach is designed as SEC OLS scheme and integrated with new modules for detecting and correcting the DAE error. The evaluation of the proposed SEC-DAEC codes in 45nm ASIC technology shows promising results. The decoding delay for protecting 16, 64, and 256 bit data words is less by at least 20% over existing SEC-DED and SEC-DAEC codes.

Text 115433.pdf - Published Version Available under License Creative Commons Attribution Non-commercial No Derivatives. Download (6MB) Official URL or Download Paper: https://ieeexplore.ieee.org/document/10813377/

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