The Design of Low Power CMOS SRAM Subsystems

The low power circuit design technique has been the trend in developing portable and smaller size electronic products, especially for communication peripherals. In the limitation on the device technology, integrated circuit design work has played an important role in performing various low power techniques. This thesis presents the design of low power Complementary Metal Oxide Semiconductor (CMOS) Static Random Access Memory (SRAM) Subsystems. CMOS technology performs much lower static power dissipation compares to other technologies. The implementation of this design by using 3.3 V supply voltage has effectively reduced the dynamic power dissipation of the circuitry. Low power is achieved by implementing 6T -memory cell. Low power techniques are also achieved on capacitance reduction by using divided word-line structure for address decoder. Finally the low power is achieved by the operating voltage reduction using current-mode sensing technique for sense amplifier with the pre-charge voltage of Vdd/2.

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