Standard cell library evaluation and optimization for near-threshold voltage operation

Near-threshold voltage (NTV) operation digital integrated circuits have come into sight in recent decades due to the need for energy-efficient design for battery-powered devices. While earning the energy benefits from the NTV operation, the challenges of the performance degradation and variability are preventing the NTV design to be widely implemented in most computing applications. Improving energy efficiency while maintaining performance becomes the primary goal for the NTV design. The standard cell library optimization should be carefully considered to achieve better energy, performance, and area of the design. This dissertation presents the joint optimization techniques of standard cell height tuning with two different transistor layout structures, namely full diffusion (FD) layout structure and inverse narrow width effect (INWE)-aware layout structure. An increased number of optimization parameters and techniques affect the evaluation efficiency of the standard cell library at the circuit level. The evaluation efficiency (i.e., synthesis runtime) requires to be improved using the modeling technique to fasten the time-consuming process while maintaining the accuracy. An area-efficiency curve modeling framework has been proposed in this dissertation to reduce the runtime to generate the area-delay tradeoff curve for the standard cell library evaluation. The tuning of standard cell height with FD layout structure results in 5.5% higher performance when using a taller cell height (i.e., 14-track) library, and 55.4% lower energy when using a shorter cell height (i.e., 7-track) library. As compared to the FD layout structure, the INWE-aware layout structure shows higher energy-delay improvement due to the INWE that reduces the threshold voltage when using a narrow width transistor. Two INWE-aware layout structures, namely multiplier and multi-finger, have also been explored in this study. The proposed reduced height (i.e., 6-track) library with multi-finger layout structure results in 16% performance improvement and 14% area improvement as compared to the 8-track multiplier library. Lastly, the proposed area-efficiency curve modeling framework can reduce about 16.5X to 18.5X of synthesis runtime with around 2.74% to 5.27% error from the uniform interval curve generation method. In conclusion, the optimal NTV-operated standard cell library in terms of energy, performance, and area can be achieved by using the lower track height multi-finger layout structure as compared to FD and multiplier layout structure. Besides, the evaluation of the standard cell library on area-performance tradeoff can be sped up through the proposed area-efficiency curve modeling framework.

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