# Development of an integrated circuit topology using multilevel inverter and matrix converter

## Citation

Al-Mahrouk, Akram Mohammed (2020) Development of an integrated circuit topology using multilevel inverter and matrix converter. Doctoral thesis, Universiti Putra Malaysia.

## Abstract

Multilevel Inverter (MI) is a device to convert Direct Current (DC) power to Alternating Current (AC) power. The MI is widely used in renewable energy applications such as Photovoltaic (PV) solar cells and wind turbine systems. The main challenges of MIs design are reducing the huge number of Component Count (CC), Total Harmonic Distortions (THD) value and power losses. These challenges are interconnected with the operation challenges such as the types of control algorithms and switching frequencies of MI which overall effect on the MI circuit design and increases the design complexity. The MI can be designed to generate a three-phase output voltage. However, most researchers are more interested in reducing the component count as a single-phase design and then tripled the circuit to generate a three-phase output voltage. Three-Time-Repetition (TTR) is a process of replicating the circuit three times to produce a three-phase output voltage from a single-phase circuit that has contributed to thrice the number of CC. Two proposed design called Voltage Selection Multilevel Inverter Matrix Converter (VSMIMC) and H-bridge Multilevel Inverter Matrix Converter (HMIMC) was used to solve the TTR problem. The Matrix Converter (MC) was used to share the three input signals into three phase output voltage. For VSMIMC the three input signals of MC ware used as following Maximum Positive Voltage (MPV), Zero Voltage (ZV) and Maximum Negative Voltage (MNV). While for HMIMC, the three input signals are Upper Positive (UP), Middle Positive (MP) and Lower Positive (LP). The operation of VSMIMC and HMIMC circuits are sophisticated when both of multilevel inverter and matrix converter are connected in series. Therefore, a new proposed control system called Voltage Selection Algorithm (VSA) was formulated to simplify the operation of the proposed circuit. In addition, mix-mode operation using VSA and Nearest Level Control (NLC) was tested to decrease the total harmonic distortions and check the performance flexibility of VSA operation. The comparison with others’ published circuits showed that the proposed VSMIMC and HMIMC had reduced the component count of MI at several different voltage levels. The VSMIMC and HMIMC circuit designs at twenty-five levels had the same number of switches, where below twenty-five levels, the VSMIMC had the lowest number of CC. However, for above twenty-five levels, the HMIMC had the lowest number of CC. The VSMIMC and HMIMC had reduced the CC switches by 75% compared to the traditional MI and 30% compared to the modern designs of MI. The seven levels circuit design of HMIMC gives Total Harmonic Distortion results of 13.38% on simulation model and 12.9% on hardware model.