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Quiescent current reduction of self-compensated low-dropout voltage regulator


Lee, Chu Liang (2019) Quiescent current reduction of self-compensated low-dropout voltage regulator. Doctoral thesis, Universiti Putra Malaysia.


Low-Dropout Voltage Regulator (LDO) is a linear regulator which is mainly used to regulate noiseless supply voltage for analog and Radio Frequency (RF) circuits. Today, the shrinking of transistor size due to the advancement of process technology and the increasing interests in the Internet-of-Thing (IoT) have increased the market demand for portable, wearable and implantable electronic devices. This has driven the need for low power Silicon-on-Chip (SoC) design which includes the integration of LDO into SoC. Analog and RF circuits have contributed to significantly high percentage of current consumption in low power SoC designs, mainly during stand-by mode. The reduction of quiescent current in analog LDO circuits become very important in order to reduce power consumption and to improve the efficiency of LDO especially during low output load current. Quiescent current is the current needed to keep LDO’s internal circuit in vigilant. However, with the absent of large off-chip compensation-capacitor for LDO in SoC, an excessive current is required to maintain ac loop stability of LDO system, especially during low output load current condition. A self-adjustable current reduction circuit technique has been proposed in this thesis to reduce this unnecessary current when output load current increases from zero value. On top of that, a self-compensation circuit technique is also been proposed to cater the worst case loop stability issue when load current reducing to zero. In this technique, the UGF has been shifted to a lower frequency away from the second pole frequency according to the amount of output load current. It is done using a current feedback circuit, where the total gain is lowered without affecting the location of dominant pole. The self compensation technique further reduces the total quiescent current, and avoid the excessive current to be used to keep the second pole at higher frequency. The proposed LDO has been designed and fabricated using 0.13μm CMOS process technology. The results has shown that the proposed LDO exhibits good stability with phase margin more than 60° for all output load condition. The LDO’s total quiescent current is only 7.4μA at zero output load current, and 17.7μA at maximum output load current of 100mA. The total quiescent current measurement result on LDO with BGR circuit is 33.1μA, where the BGR consumed 20μA. This LDO is functional at 1.20V supply voltage with 200mV dropout voltage.

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Additional Metadata

Item Type: Thesis (Doctoral)
Subject: Low voltage integrated circuits - Design and construction - Case studies
Subject: Electric current regulators - Design and construction
Subject: Iddq testing
Call Number: FK 2020 15
Chairman Supervisor: Roslina Mohd Sidek, PhD
Divisions: Faculty of Engineering
Depositing User: Mas Norain Hashim
Date Deposited: 29 Jun 2021 06:07
Last Modified: 06 Dec 2021 04:52
URI: http://psasir.upm.edu.my/id/eprint/89883
Statistic Details: View Download Statistic

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