Development of low power viterbi decoder on complex programmable logic device platform

Space Time Trellis Code (STTC) and Viterbi algorithm combinations are known to offer a robust forward error correction system. This especially has been used in a noisy digital communication system such as wireless communication. A traditional Viterbi decoder would contain three main units; Branch Metric Computation Unit (BMC), Add Compare Select Unit (ACS) and path metric updater (PMU). This combination of STTC and Viterbi algorithm however will cause a complexity in STTC decoder and increase power consumption of the system in addition to reducing battery life of portable devices. The objectives of this study are to analyse high power consumption in the STTC Viterbi decoder, design low complexity model of the ACS and the PMU for STTC Viterbi decoder and develop low power 0.18μm CMOS Viterbi decoder for STTC. For the decoder, maximum likelihood sequence estimation (MLSE) method has been used in the proposed Viterbi decoder in order to find the highest probability that is selected from all possible transmitted bit sequences which are nearest to the received sequences. ACS and PMU have been reported in previous findings to consume most power of decoder. This thesis thus proposes suitable methods to reduce power consumption in Viterbi decoder by enhancing the ACS and PMU module. For ACS, the traditional method of Viterbi algorithm is to add the previous state metric with the current branch metric, compare the new branch metric and select the minimum branch metric. This thesis however proposes to remove the “Add” function in this Viterbi algorithm by comparing the minimum value of branch metric from the four states of branch metrics, selecting the minimum values and encoding the minimum branch metrics. For the path metric updater unit (PMU), the traditional method of Viterbi algorithm is to store the selected minimum value of branch metric in the memory unit. After the computation completes, the traceback unit will go back to the previous memory path to read and decode the minimum path metrics that have been stored by ACS unit. This thesis also proposes to remove the add unit in the ACS and traceback unit in the PMU and replaces it with decoded unit by decoding the code values directly from ACS unit. Moreover, the new algorithm by reducing the complexity of the tradit ional Viterbi without compromising the performance of the STTC Viterbi decoder has been proposed. Consequently, the number of logic gates and the total power consumption of the STTC Viterbi decoder can be reduced by using the new algorithms. The proposed algorithms have been designed and implemented by using MATLAB, Altera Quartus 2 and Altera MAX V CPLD board. Hence, all results are shown through bit error rate, device utilization, and functional simulation to show the functionality of the hardware design and total power consumption. Results show that more than 43% of the power consumption has been reduced compared to the previous STTC Viterbi decoder designs and achieved 50 MHz clock for 4-PSK modulations.

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