Design and implementation of low complexity OFDM modulator for broadband wireless devices

The modulation technique plays significant role as a component of communication systems. A novel technique known as orthogonal frequency division multiplexing (OFDM), which can be implemented in broadband wireless systems, has been designed and developed to fulfill the requirements of high data rate signals. One of the major drawbacks of OFDM systems is its high crest factor (CF) in the time domain. The large CF causes the transmit power amplifier to enter the non-linear region, distorting the signal and resulting in a significant increase in the bit error rate (BER) at the receiver. This thesis focuses on the design and implementation of a proposed techniques approach to reduce CF, and the computational complexity of the proposed techniques will increase linearly with the increase of the number of subcarriers. This research presents three novel low complexity techniques for reducing CF in OFDM systems followed by an efficient hardware co-simulation implementation of two of these techniques by using a Xilinx system generator on a field programmable gate array (FPGA). The first part of this thesis presents a new subblocks interleaving partial transmit sequence (SBI-PTS) technique having low complexity for reducing the CF in OFDM systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on a field programmable gate array (FPGA). In this technique, a new subblocks interleaver is proposed. The subblocks interleaver can be applied in the frequency domain before the inverse fast Fourier transforms (IFFT) or in the time domain after (IFFT). Moreover, a new optimization scheme is introduced, in which the number of iterations is made to be equal to the number of subblocks only which results in reduced processing time and less computation that leads to reduced complexity. A new low complexity high efficiency hybrid multiplicative-additive CF reduction technique for OFDM systems is presented in the second part of the thesis. This technique consists of two IFFT blocks. First, the output of the two IFFT blocks is partitioned into four subblocks, which are subsequently used to rearrange the subblocks with padding zeros in a specific manner. Then, a new optimization scheme is introduced, in which only a single two-phase sequence and four iterations needs to be applied. Numerical analysis shows that the hybrid proposed technique achieves better CF reduction performance with significantly lower complexity and better bit error rate performance than the existing scrambling (multiplicative) and additive CF techniques. The other salient feature of this scheme is that no side information (SI) is needed which increases transmission efficiency. The last part of this thesis presents a new low complexity scrambling technique for reducing the CF in OFDM systems followed by an efficient hardware cosimulation implementation of this technique by using a Xilinx system generator on a FPGA. In this technique, the output of a single IFFT is duplicated M times and partitioned into M subblocks, which are subsequently interleaved. Then, a new optimization scheme is introduced in which only a single two phase sequence need to be applied. Unlike the C-PTS which needs M- IFFT blocks and 2M-1 iterations, the proposed technique requires only a single IFFT block and M iterations. These features significantly reduce processing time and less computation that leads to reduced complexity. Simulation results demonstrate that the new technique can effectively reduce the complexity up to 99:95% compared with the conventional PTS (C-PTS) technique and yields good CF performance.

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