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Numerical investigation of channel width variation in junctionless transistors performance


Dehzangi, Arash and Larki, Farhad and Yeop Majlis, Burhanuddin and Hamidon, Mohd Nizar and N V Visvanathan, P. Susthitha Menon and Jalar @ Jalil, Azman and Islam, Md. Shabiul and Md. Ali, Sawal Hamid (2013) Numerical investigation of channel width variation in junctionless transistors performance. In: 2013 IEEE Regional Symposium on Micro and Nano Electronics (RSM 2013), 25-27 Sept. 2013, Langkawi, Kedah, Malaysia. (pp. 101-104).


Double gate junctionless (DGJLT) transistor, as a pinch off device, was previously fabricated. In this letter, the impact of channel width variation on behaviour of the device is studied by means of 3D-TCAD simulation tool. In this matter, the transfer characteristics, energy band diagram (valence/conduction band) and normal electric field along the nanowire between the source and the drain are studied at pinch off state. By decreasing the nanowire width, the on current decreases. Threshold voltage also reduced by decreasing the wire width. The highest electric field occurs at off state and the normal component of the electric field is stronger for smaller channel width. At pinch off state, the energy band diagrams revealed that a potential barrier against the current flow was built in channel which the smallest width has higher potential barrier. The overall result agrees with the behaviour of the nanowire junctionless transistors.

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Additional Metadata

Item Type: Conference or Workshop Item (Paper)
Divisions: Institute of Advanced Technology
DOI Number: https://doi.org/10.1109/RSM.2013.6706483
Publisher: IEEE
Keywords: Lateral gate junctionless transistor; Energy band diagram; Channel width effect; TCAD simulation
Depositing User: Nabilah Mustapa
Date Deposited: 12 Jun 2019 07:36
Last Modified: 12 Jun 2019 07:36
Altmetrics: http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/RSM.2013.6706483
URI: http://psasir.upm.edu.my/id/eprint/69155
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