Design of 8-bit SAR-ADC CMOS

Citation

Hassan, Hur A. and Abdul Halin, Izhal and Aris, Ishak and Hassan, Mohd Khair (2009) Design of 8-bit SAR-ADC CMOS. In: 2009 IEEE Student Conference on Research and Development (SCOReD 2009), 16-18 Nov. 2009, UPM, Serdang, Selangor. (pp. 272-275).

Abstract

Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18μm CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic circuit and digital-to-analog conversion consists of binary weighted capacitor arrays for the differential inputs. The ADC has INL and DNL of 0.45 LSB for supply voltage 1.8V, at sampling rate 200 KS/S and signal to noise ratio distortion is 58.5 dB. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SOC) circuit designs.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/SCORED.2009.5443038
Publisher:	IEEE
Keywords:	Analog-to-digital converter; CMOS; Comparator; Digital-to-analog converter; Low voltage; Sample-and-hold
Depositing User:	Nabilah Mustapa
Date Deposited:	11 Jun 2019 02:02
Last Modified:	11 Jun 2019 02:02
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/SCORED.2009.5443038
URI:	http://psasir.upm.edu.my/id/eprint/68879
Statistic Details:	View Download Statistic

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