Effective implementation of AES-XTS on FPGA

Citation

Ahmed, Shakil and Samsudin, Khairulmizam and Ramli, Abdul Rahman and Rokhani, Fakhrul Zaman (2011) Effective implementation of AES-XTS on FPGA. In: 2011 IEEE Region 10 Conference (TENCON 2011), 21-24 Nov. 2011, Bali, Indonesia. (pp. 184-186).

Abstract

This paper proposes an effective FPGA implementation for data storage encryption. Throughput, area and power consumption are the most important parameters to evaluate any FPGA implemented design. Our proposed design not only achieves a high throughput but also a considerable amount of throughput/area that is better compared to current implementations. The proposed implementation gives a memory based pipelined architecture. The design achieves a throughput of 5.25 Gb/sec that is relatively better than any other FPGA implementation to date. Xilinx ISE 10.1 is used as a design tool and Verilog HDL is used to code the design.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/TENCON.2011.6129088
Publisher:	IEEE
Keywords:	Component; AES-XTS; Cryptography; Discryption; FPGA
Depositing User:	Nabilah Mustapa
Date Deposited:	10 Jun 2019 03:34
Last Modified:	10 Jun 2019 03:34
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/TENCON.2011.6129088
URI:	http://psasir.upm.edu.my/id/eprint/68776
Statistic Details:	View Download Statistic

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