Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus

Citation

Mai, Yoong Ching and Ang, Tun Boon and Chin, Kock Yeong and Rokhani, Fakhrul Zaman (2010) Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus. In: 2010 Asia Pacific Conference on Circuit and System (APCCAS 2010), 6-9 Dec. 2010, Kuala Lumpur, Malaysia. (pp. 1143-1146).

Abstract

In this paper, the technique of optimal interconnects width and spacing is analyzed to reduce the area, delay and area-delay-product of multi-level signaling on-chip bus. To capture the delay impact from cross-coupling capacitance in the deep sub-micron on-chip bus, the Miller Capacitance Factor (MCF) for 4-level signals is developed. Results show that our proposed technique reveals the trade-off between bus area and delay to achieve the optimized bus configuration.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/APCCAS.2010.5775086
Publisher:	IEEE
Keywords:	Multilevel signaling; Interconnect delay; Interconnect optimization; Coupling capacitance
Depositing User:	Nabilah Mustapa
Date Deposited:	10 Jun 2019 02:43
Last Modified:	06 Jul 2020 07:14
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/APCCAS.2010.5775086
URI:	http://psasir.upm.edu.my/id/eprint/68598
Statistic Details:	View Download Statistic

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