Numerical study of side gate junction-less transistor in on state

Citation

Dehzangi, Arash and Larki, Farhad and Yeop Majlis, Burhanuddin and Hamidon, Mohd Nizar and Navasery, Manizheh and Gharibshahi, Elham and Khalilzadeh, Nasrin and Vakilian, Mohammadmahdi and Saion, Elias (2013) Numerical study of side gate junction-less transistor in on state. In: 2013 IEEE Regional Symposium on Micro and Nano Electronics (RSM 2013), 25-27 Sept. 2013, Langkawi, Kedah, Malaysia. (pp. 398-401).

Abstract

Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in on state for zero gate voltage in depletion mode. Negative gate voltage drives the device into on state, but unable to make significant effect on drain current as accmulation mode. Simulation results for valence band energy, electric field and hole density are investigated along the active regions. The influence of the electric field due to the applied voltages of V DS and V G on charge distribution is much more when the device operates at the saturation region. The hole quasi-Fermi level has a positive slope showing the current flows from source to drain.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Science Institute of Advanced Technology
DOI Number:	https://doi.org/10.1109/RSM.2013.6706575
Publisher:	IEEE
Keywords:	Side gate junctionless transistors (SGJLT); Valence band energy; Hole density distribution
Depositing User:	Nabilah Mustapa
Date Deposited:	09 May 2019 01:42
Last Modified:	09 May 2019 01:42
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/RSM.2013.6706575
URI:	http://psasir.upm.edu.my/id/eprint/68136
Statistic Details:	View Download Statistic

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