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FPGA-enabled binarised convolutional neural networks toward real-time embedded object recognition system


Citation

Shuto, Daisuke and Abbas, Z. and Sulaiman, N. and Tamukoh, H. (2017) FPGA-enabled binarised convolutional neural networks toward real-time embedded object recognition system. In: 5th International Symposium on Applied Engineering and Sciences (SAES2017), 14-15 Nov. 2017, Universiti Putra Malaysia. (p. 7).

Abstract

In this presentation, we report the results of applying a binarised Convolutional Neural Network (CNN) and a Field Programmable Gate Array (FPGA) for image-based object recognition. While the demand rises for robots with robust object recognition implemented with Neural Networks, a trade-off between data processing rate and power consumption persists. Some applications utilise GPGPU (General Purpose computing on Graphics Processing Units), which results in high power consumption thus undesirable for embedded systems, while the others communicate with cloud computers to minimise computational resources at the clients’ side, i.e. robots, raising another concern that the robots are unable to perform object recognition without the servers and network connections. To overcome these difficulties, we propose an embedded object recognition system implemented with a binarised CNN and an FPGA. FPGAs consist of a matrix of reconfigurable logic gates allowing parallel computing which befits most image processing algorithms such as the CNN. We train the binarised CNN on one of our datasets that contain images of several kinds of food and beverages. The results of the experiments show that the binarised CNN with an FPGA maintains high accuracy as well as real-time computation, suggesting that the proposed system is suitable for robots to perform their tasks in a real-world environment without needing to communicate with a server.


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Additional Metadata

Item Type: Conference or Workshop Item (Poster)
Divisions: Faculty of Engineering
Keywords: Binarised convolutional neural network (CNN); Field programmable gate array (FPGA); Object recognition
Depositing User: Nabilah Mustapa
Date Deposited: 04 Jul 2018 02:38
Last Modified: 04 Jul 2018 02:38
URI: http://psasir.upm.edu.my/id/eprint/64363
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