Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology

Citation

Shafie, Suhaidi and Md Yunus, Nurul Amziah and Ong, Wei Chiek and Wang, Chee Yew and Abdul Halin, Izhal (2017) Analog signal path circuit for a four transistor pixel in standard 0.13μm CMOS technology. In: 2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 31 Oct.-2 Nov. 2017, Kuala Lumpur, Malaysia. (pp. 133-136).

Abstract

This project is aimed to develop the layout for the analog signal path of a 4 transistor pixel CMOS image sensor using EDA tools in standard 0.13μm Silterra fabrication technology. The sub-circuit blocks that define the analog input-output path consists of the 320×240 pixel array, 320 column parallel correlated double sampling circuits, an output buffer amplifier and all associated bias circuitry. Each pixel size has a dimension of 10μm × 10μm. The pixel's frame rate is targeted to be 120 frames per second (fps) working in a QVGA picture format (320× 240 pixels). From simulation, the illumination range of 0.01 lux to 0.25 lux has been tested and shows only a 2.8% error from the ideal output linearity.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/PRIMEASIA.2017.8280382
Publisher:	IEEE
Keywords:	CMOS image sensor; Slow motion video; 4T pixel; Active pixel sensors
Depositing User:	Nabilah Mustapa
Date Deposited:	05 Mar 2018 07:12
Last Modified:	05 Mar 2018 07:12
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/PRIMEASIA.2017.8280382
URI:	http://psasir.upm.edu.my/id/eprint/59445
Statistic Details:	View Download Statistic

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