Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip

Citation

Zakaria, Fazrul Faiz and Abdul Latiff, Nurul Adilah and Hashim, Shaiful Jahari and Ehkan, Phaklen and Rokhani, Fakhrul Zaman (2016) Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip. In: 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 25-28 Oct. 2016, Jeju, South Korea. (pp. 358-361).

Abstract

In this paper, the FPGA architecture having a hardwired network-on-chip (NoC) as system-level interconnect resource with adaptive router to support ranges of traffic condition. The proposed adaptive routers cooperatively allocate the virtual channel to minimizes the cost of supporting a wide range of traffic requirements from various FPGA application design instances. Simulation results show performance augmentation of 25% on average over an equal-size standard router, or achieve iso-performance using 50% less virtual channel buffer size.

Download File

Preview

Text (Abstract)
Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip.pdf
Download (34kB) | Preview

Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/APCCAS.2016.7803975
Publisher:	IEEE
Keywords:	Adaptive; FPGA; Hardwired; NoC
Depositing User:	Nabilah Mustapa
Date Deposited:	02 Mar 2018 03:30
Last Modified:	02 Mar 2018 03:30
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/APCCAS.2016.7803975
URI:	http://psasir.upm.edu.my/id/eprint/59421
Statistic Details:	View Download Statistic

Actions (login required)

View Item