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A low power multiplexer based pass transistor logic full adder


Kamsani, Noor Ain and Thangasamy, Veeraiyah and Hashim, Shaiful Jahari and Yusoff, Zubaida and Bukhori, Muhammad Faiz and Hamidon, Mohd Nizar (2015) A low power multiplexer based pass transistor logic full adder. In: 2015 IEEE Regional Symposium on Micro and Nano Electronics (RSM 2015), 19-21 Aug. 2015, Primula Beach Hotel, Kuala Terengganu. .


In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10-18 J and its power consumption is 2.01μW. The proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation. The proposed adder when cascaded in a 4-bit ripple carry adder configuration, its power, delay and PDP performance are better than the other adders making it suitable for larger arithmetic circuits.

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Additional Metadata

Item Type: Conference or Workshop Item (Paper)
Divisions: Faculty of Engineering
Institute of Advanced Technology
DOI Number: https://doi.org/10.1109/RSM.2015.7354994
Publisher: IEEE
Keywords: Delay; Full adder; Low power; Multiplexer; Pass transistor logic; Power delay product (PDP)
Depositing User: Nabilah Mustapa
Date Deposited: 03 Jul 2017 09:36
Last Modified: 03 Jul 2017 09:36
Altmetrics: http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/RSM.2015.7354994
URI: http://psasir.upm.edu.my/id/eprint/56112
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