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The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model


Citation

Abu, Mohd Azlan and Harun, Harlisya and Harmin, Mohammad Yazdi and Abdul Wahab, Noor Izzri and Abdul Kadir, Muhd Khairulzaman (2016) The design of viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model. World Journal of Engineering, 13 (6). pp. 540-546. ISSN 1708-5284; ESSN: 1708-5284

Abstract / Synopsis

Purpose – This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). Design/methodology/approach – The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm. Findings – The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps. Originality/value – It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.


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Additional Metadata

Item Type: Article
Divisions: Faculty of Engineering
DOI Number: https://doi.org/10.1108/WJE-09-2016-0088
Publisher: Emerald Group Publishing
Keywords: Space time trellis code; Viterbi decoder
Depositing User: Nida Hidayati Ghazali
Date Deposited: 27 Nov 2017 14:12
Last Modified: 27 Nov 2017 14:12
Altmetrics: http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1108/WJE-09-2016-0088
URI: http://psasir.upm.edu.my/id/eprint/52962
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