Reduced hardware architecture for energy-efficient IoT healthcare sensor nodes

Citation

Lim, Yang Wei and Daas, Sreedharan Baskara and Hashim, Shaiful Jahari and Mohd Sidek, Roslina and Kamsani, Noor Ain and Rokhani, Fakhrul Zaman (2015) Reduced hardware architecture for energy-efficient IoT healthcare sensor nodes. In: 2015 IEEE International Circuits and Systems Symposium (ICSyS 2015), 2-4 Sept. 2015, Holiday Villa Beach Resort & Spa, Langkawi, Kedah. (pp. 90-95).

Abstract

Healthcare solutions through the introduction of wearable healthcare devices are benefitting from Internet of Things technology. Though these small form-factor wearable devices promise great benefits, guaranteeing long device operating lifetime is yet the biggest challenge due to high-energy consumption. In this paper, a reduced hardware architecture system-on-chip targeting digital block design was proposed higher energy efficiency. The design has been verified by synthesizing into FPGA and implemented in silicon based on Silterra 180nm process. Results show that the proposed design achieved reduction up to 24% of leakage power and 15% of dynamic power reduction over reference design. In addition, 24.3% of excessive area was reduced by using the proposed reduced hardware architecture technique.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/CircuitsAndSystems.2015.7394071
Publisher:	IEEE
Keywords:	ASIC; Energy-efficient; FPGA; Internet of Things; Microcontroller
Depositing User:	Nabilah Mustapa
Date Deposited:	14 Jul 2016 05:03
Last Modified:	12 Jun 2019 01:51
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/CircuitsAndSystems.2015.7394071
URI:	http://psasir.upm.edu.my/id/eprint/47697
Statistic Details:	View Download Statistic

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