Design of radix-4 single path delay fast fourier transform processor with genetic algorithms optimization

This research work involves the implementation of Single Objective Genetic Algorithm (SOGA) and Multi-objectives Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor. The FFT processor is a critical block widely used in digital processing, which is considered as a very power consuming block in a device as many data are inputted for the FFT computation. Nowadays, the portability of the electronic devices which uses FFT processor requires being smaller size and low power consumption. One of the methods is to reduce the word length of FFT during its usage. However, the reduction of word length of FFT processor will degrade its Signal to Noise Ratio (SNR) value. The SNR value represents the accuracy of the FFT processor. The larger the word length of the FFT processor, the higher the SNR value, leading to higher Switching Activity (SA), thus increases the power consumption of the FFT processor. In this research, the Genetic Algorithms (GA) is used to optimize the word length of FFT coefficients to maintain the SNR value and reduce the SA at the same time. The genetic algorithms is proven to be a very effective method in optimization by using the way imitating natural process of living beings such as crossover, mutation and selection. The Multi Objective Genetic Algorithms (MOGA) is capable of optimizing the problem which has more than one criterion and both criterions must be treated simultaneously. In this work, the GA optimization is implemented in the twiddle factor of FFT processor. The output solutions performance of the GA optimized FFT is compared to the non-GA solutions. The target of the optimization is to reduce the FFT word length and at the same time the solutions must fulfil the requirement of SNR higher than 63 dB and SA lower the conventional FFT which is 192 times. The results show that, the SOGA capable to optimize the FFT SNR without considering the word length. The MOGA can successfully optimize the performance of FFT by SNR and reducing the word length to 13 bits. Two MOGA methods are used; they are Weighted Sum approach and Non-dominated Sorting Approach. The Weighted Sum approach is more suitable to be implemented in the optimization as it is simpler compared to Non-dominated Sorting Approach.

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