Dynamic noise analysis for 4-PAM signaling scheme

For the past two decades, the feature size in the integrated circuits industry has been shrinking continuously. The higher number of gates integrated on a die has been translated into soaring demand for on-chip communication. Different multilevel signaling techniques with and without bus encoding or error control coding have been proposed to deal with the tradeoffs between reliability and power consumption. However, the signal integrity analysis to evaluate these techniques has been often performed based on pessimistic static noise margins. By applying dynamic noise margins, in this paper, we propose a new method to model the receivers in 4- PAM signaling scheme as one of popular alternatives for binary signaling. The outcome of this research demonstrates significant improvement in predicting the reliability performance of the chosen signaling scheme. The more realistic signal integrity analysis presented here can be utilized in favor of various design optimizations, for example, shorter spaces between wires, longer interconnects, faster transitions and lower signaling voltages.

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