Development of a Functional Digital Integrated Circuit Testing System Using Mixed-Mode Technique

With the continuous increase in design complexities and packing densities of integrated circuit (IC), problems associated with conventional Automatic Test Equipment (ATE)-based IC testing approach have become a burning issue in the semiconductor world, which needs an economic solution with reliable performance. Recently, the superiority of Dynamic Reseeding-based Mixed-mode (DRM) technique has been proven over all other existing test techniques in the Built-in Self-Test (BIST) environment. This thesis introduces the implementation of the DRM technique in a system-on-a-chip (SOC) in alleviating the problems of conventional ATE-based external testing of digital IC. The performance of the SOC in IC testing has been verified using fault simulation experiments on the ISCAS85 benchmark circuits (Circuits proposed in the International Symposium on Circuits and Systems in 1985). Significant improvement is observed in achieving complete fault coverage for the ISCAS85 benchmark circuits using acceptable number of test vectors. Fault simulation results show that the proposed DRM technique produces 100% fault coverage for the benchmark circuits c432, c1355, c1908, c2670, c3540 and c5315 using the 232, 526, 996, 336, 360 and 748 test cubes, respectively which are much lower than the numbers from the approaches suggested by other researchers. It also offers much lower data storage requirements in IC testing than the conventional ATE-based testing approach. The results show that 2 to 11 times less memory is needed for testing the ISCAS85 benchmark circuits using the DRM technique than that of the deterministic testing approach. Verilog Hardware Description Language (HDL), which is an industry standard IC design tool, has been used to design the SOC proposed in this thesis. Main modules of the SOC are micro-UART (Universal Asynchronous Receiver and Transmitter), a controller, pattern generator, signature analyzer (SA), instruction registers and Random Access Memories (RAMs). A prototype test set-up has been developed for testing IC by implementing the design of the SOC into a Field Programmable Gate Array Logic (FPGA) chip and then by interfacing the FPGA chip with a personal computer (PC) through a Graphical User Interface (GUI). For testing a circuit, necessary test information is loaded into the SOC and the testing process is executed using the GUI from the PC. The SOC goes into autonomous mode. It generates test vectors, applies them to the Circuit Under Test (CUT) and captures the output responses and sends it into the SA for compression. At the end of testing, the generated signature is compared with that of a reference circuit (fault-free circuit of the same type) and the CUT is identified as fault-free if the two signatures are the same and as faulty if otherwise. The operation of the SOC has been verified in real time by testing a 16-bit multiplier as a sample CUT. It is user programmable, which increases flexibility and reliability in IC testing. It is capable of testing functionality of combinational circuits as well as sequential circuits with scan-path facility.

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