Design of a high speed and low latency crypto-processor ASIC

Citation

Ali, Md. Liakot and Roy, Niranjan and Faisal, Fazle Elahi and Mohd Ali, Mohd Alauddin and Aris, Ishak (2008) Design of a high speed and low latency crypto-processor ASIC. In: 2008 IEEE International Conference on Semiconductor Electronics (ICSE 2008), 25-27 Nov. 2008, Johor Bahru, Malaysia. (pp. 96-98).

Abstract

This paper presents the design of an ultra high speed crypto-processor for next generation IT security. It addresses the next generation IT security requirements: the resistance against all attacks and high speed with low latency. The proposed processor is capable of generating cryptographically secured information at a rate of multi-ten Gbps. The performance of the processor is compared with that of other researchers which proves it's superiority over them.

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Additional Metadata

Item Type:	Conference or Workshop Item (Paper)
Divisions:	Faculty of Engineering
DOI Number:	https://doi.org/10.1109/SMELEC.2008.4770284
Publisher:	IEEE
Keywords:	Crypto-processor; High speed; Low latency; ASIC
Depositing User:	Nabilah Mustapa
Date Deposited:	10 Aug 2020 02:23
Last Modified:	10 Aug 2020 02:23
Altmetrics:	http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/SMELEC.2008.4770284
URI:	http://psasir.upm.edu.my/id/eprint/37530
Statistic Details:	View Download Statistic

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