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Optimality of bus-invert coding


Rokhani, Fakhrul Zaman and Kan, Wen Chih and Kieffer, John and Sobelman, Gerald E. (2009) Optimality of bus-invert coding. IEEE Transactions on Circuits and Systems II: Express Briefs, 55 (11). pp. 1134-1138. ISSN 1549-7747; ESSN: 1558-3791


Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribution is from the self-capacitance of the wires. This algorithm uses an invert line to signal whether the bus data are in its original or an inverted form. While the method appears to be a greedy algorithm, we show that it is, in fact, an optimal strategy. To do so, we first represent the bus and invert line using a trellis diagram. Then, we show that applying bus-invert coding to a sequence of words gives the same result as would be obtained by using the Viterbi algorithm, which is known to be optimal. We also show that partitioning an M-bit bus into P subbuses and using bus-invert coding on each subbus can be described as applying the Viterbi algorithm on a 2P-state trellis.

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Additional Metadata

Item Type: Article
Divisions: Faculty of Engineering
DOI Number: https://doi.org/10.1109/TCSII.2008.2002564
Publisher: Institute of Electrical and Electronics Engineers Inc.
Keywords: Bus coding; Low power; Off-chip buses; Trellis diagram; Viterbi decoding.
Depositing User: Fatimah Zahrah @ Aishah Amran
Date Deposited: 15 Oct 2014 03:36
Last Modified: 30 Oct 2015 02:22
Altmetrics: http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/TCSII.2008.2002564
URI: http://psasir.upm.edu.my/id/eprint/15953
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