A PVT-robust 0.8 V subthreshold double-tail dynamic comparator with 20.7 fJ/comparison-step energy efficiency for 10-bit SAR ADCs

Dynamic comparators are key building blocks in low-power successive-approximation-register (SAR) analog-to-digital converters (ADCs), where energy efficiency, decision speed, and reliable operation under process, voltage, and temperature (PVT) variations are essential design requirements. This paper presents a 0.8 V subthreshold double-tail dynamic comparator incorporating a threshold-controlled latch activation mechanism for differential 10-bit SAR ADC applications. By delaying latch regeneration until sufficient differential voltage amplification is established by the dynamic amplifier stage, the proposed architecture suppresses premature regeneration, reduces kickback-induced disturbances, and improves comparator operation under low-voltage conditions. To comprehensively evaluate robustness under extreme operating conditions, a dedicated Input Test Pattern (ITP)-based validation methodology was developed and applied across 45 PVT corners comprising TT, SS, FF, FS, and SF process conditions, ±10% supply-voltage variation (0.72–0.88 V), and temperatures ranging from 0 °C to 100 °C. The comparator was implemented in a 180 nm CMOS technology and evaluated through schematic and post-layout simulations. Under nominal operating conditions, the proposed comparator resolved a minimum differential input voltage of 0.8 mV while achieving a post-layout regeneration delay of 327 ps, an average power consumption of 41.4 nW, and an energy efficiency of 20.7 fJ/comparison-step. In addition, the proposed architecture achieved a peak-to-peak kickback noise of 197 mV and successfully passed all 45 post-layout PVT corner simulations, demonstrating reliable functionality under wide process, voltage, and temperature variations. These results validate the effectiveness of the proposed threshold-controlled latch activation mechanism and the ITP-based validation methodology, demonstrating that the proposed JRR2 comparator provides an effective balance among low-voltage operation, decision speed, ultra-low-power consumption, energy efficiency, and robustness for differential 10-bit SAR ADC applications.

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