A new framework for multi-partition finite state machine low power design based on genetic algorithm

At present, the power consumption of digital systems receives substantial attention due to the demand for long-lasting batteries for portable devices, such as cameras, smartphones, and various electronic gadgets. These devices are control based and keep running throughout their lifetime. Given that most of these devices use digital controllers implemented as finite-state machines (FSMs), the reduction of an FSM's power consumption is essential. FSMs can control a simple transmission or control different components of an extensive system on chip design. High-level low-power design techniques are used to reduce the power consumption of digital circuits. Many researchers use a variety of algorithms to optimize a solution. Among these methods is the genetic algorithm (GA)-based optimization, that technique shows a high performance to reduce FSM power consumption. Partitioning is one of the high-level low-power techniques which reduces FSM power consumption by dividing the logic of the FSM into smaller areas of active and inactive circuits. Therefore, the activation of smaller areas of logic circuits at a time reduces the total power consumption of the FSM. Partitioning of two areas (bi-partitioning) used in conjunction with the GA methods reduces the power consumption of FSMs. Advancements in low-power implementation methods such as power-gating and clock-gating in semi-custom IC design guarantees the practicality of the methods used for partitioning. Therefore, by using such techniques, an innovative multi-partitioning solution can be achieved for a low-power FSM design using the GA algorithm. This dissertation proposes a new framework to a multi-partitioning approach to implement FSMs, which aims to improve low power design. Multi-partitioning reduces the power consumption of an FSM by increasing the number of partitions. Therefore, the logic for each partition becomes smaller and accordingly reduces the power consumption of the FSM. However, by increasing the number of partitions, the overhead of powering control circuitries increases for each new partition to the logic circuit. Experimental results performed to a set of selected benchmarks shows the power consumption saving for each FSM topology tested. This thesis compares novel approaches to multipartition an FSM alongside standard methods using readily accepted benchmark tests. Standard monolithic and bi-partitioned forms are tested to validate the findings of previous studies. Then accordingly, this study makes a comparison between those results and multi-partitioned results. Experimental results show that the multi-partitioning methods innovated in this study are effective at reducing the power consumption of FSMs. Furthermore, reports a threshold limit to the number of partitions practically made to certain types of circuit, this is due to the overhead power consumption of the control logic, whereby over-partitioning may exceed the total power consumption of bi-partitioned FSM and monolithic FSM. In conclusion, this study successfully applies innovated FSM circuit topologies to selected FSM benchmark tests which report a more significant power consumption reduction compared with monolithic FSM power consumption and conventional bi-partitioning GA methods. This approach consistently improves the results of the GA process and shows reliable performance regarding power optimization.

Text SEYED HOSSEIN MASOUMI DEZFOULI -IR.pdf Download (3MB)

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