Optimization of Digital Electronic Circuit Structure Design Using Genetic Algorithm

Chong, Kok Hen (2008) Optimization of Digital Electronic Circuit Structure Design Using Genetic Algorithm. PhD thesis, Universiti Putra Malaysia.

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Abstract

The complexity of the digital electronic circuit is due to the number of gates used per system as well as the interconnection of the gates. Diminution of the total number of gates used and interconnection in the system would reduce the cost in the design, as well as increasing the efficiency of the overall system. As a result, the higher integration level, the better and the cheaper final product produced. The conventional digital circuit design method is based on Boolean algebra. There are no specific procedure to choose the right theorem or postulate for the Boolean expression simplification and it is very impractical to design the digital circuits that have more than four variable. Karnaugh map can provide the simple minimization process for Boolean expression, but it encounters difficulties when the variable is more than four In this research, Genetic Algorithm (GA) technique is used as a tool to search for the optimal solution for the digital circuit structure. The GA process (Inter Loop GA), crossover operator (Fix Multiple Point Crossover), mutation operator (Random Discrete Mask Mutation) and fitness function (Constraint Fitness and Gate Optimization Fitness) were developed in this research. The simulator called Optimal Digital Circuit Structure Designer (ODCSD) is also developed in this work. ODCSD is a digital circuit structure design simulation program. Further more, a prototype hardware has been designed and constructed to test the success chromosome string, which called as GA based Logic Implementer (GALI). GALI is programmed by the success chromosome bits obtained from the simulation phase. This chromosome bits are used to set up the gates arrangement in the hardware. A number of experiments are implemented to design 3-bit, 4-bit, 5-bit and 6-bit circuits. The results show that the proposed method is able to produce the optimized circuit with lesser number of gates compared to the conventional methods. In the future development, the proposed system can be used as the discrete controller when it implemented in the process control application.

Item Type:Thesis (PhD)
Chairman Supervisor:Associate Professor Ishak Aris, PhD
Call Number:FK 2008 82
Faculty or Institute:Faculty of Engineering
ID Code:7292
Deposited By: Nur Izzati Mohd Zaki
Deposited On:15 Jun 2010 09:04
Last Modified:27 May 2013 07:34

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