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Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

Lee, Lini @ Lini Lee (2001) Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture. Masters thesis, Universiti Putra Malaysia.

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Abstract

Programmable digital signal processors (pDSP) are microprocessors that are specialized to perform well in digital signal processing-intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing can be carried out and computational units can be integrated into the core with ease. In order to gain most benefit from the architecture, "Field Programmable Gate Array" (FPGA) technology can be used. FPGA technology is a technology, which gives the designer high flexibility in pDSP design. In order to fulfill the requirement of pDSP, "Very Long Instruction Word" (VLIW) architecture concept is used. Using, VHDL (Very-High-Speed-Integrated-Circuit Hardware Description Language) as design tool has the advantage in optimizing the pDSP hardware requirement with ease where varying the size of units such as register files (RF), program sequencer (PS), data address generator (DAG), arithmetic logic unit (ALU), multiply-accumulator (MAC) and shifter can be done by changing the data width or bit values. This flexibility of changing the data width or bit values is suitable in VLIW architecture approach. Based on the functional verification, the designed pDSP is able to perform mathematical operations required in signal processing. The speed of the operation is dependent on the size of the datapath as well as the type of FPGA chips. It has been shown that changing the data width or bit values in the VHDL source code of the subsystem can easily change the subsystems' sizes. Thus, the time for redesign is significandy shorten. Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). However, higher MIPS value can be achieved by using higher performance FPGAIPLO chip. Therefore, it is shown that VUW architecture concept is suitable for microprocessor architecture and the pDSP core is proven to be flexible in terms of size variation of the subsystems consequently the variation of the operation speed.

Item Type:Thesis (Masters)
Subject:Digital electronics
Subject:Architecture and technology
Chairman Supervisor:Dr. Bambang Sunaryo Suparjo
Call Number:FK 2001 42
Faculty or Institute:Faculty of Engineering
ID Code:11027
Deposited By: Nur Kamila Ramli
Deposited On:10 Jun 2011 07:25
Last Modified:19 Jul 2011 03:20

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