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Low power multicarrier- code division multiple access receiver on field programmable gate array


Mohd Hassan, Siti Lailatul and Sulaiman, Nasri and Saparon, Azilah and Mohd Yussoff, Yusnani and Jaafar, Haslina (2019) Low power multicarrier- code division multiple access receiver on field programmable gate array. International Journal of Advanced Trends in Computer Science and Engineering, 8 (1 spec. 6). pp. 318-323. ISSN 2278-3091


This paper presents a low power multi-carrier code division multiple access (MC-CDMA) receiver on field-programable gate array (FPGA). Most of the wireless application nowadays such as wireless sensor networks, portable computation and many more require a low power design. Time-division multiple access (TDMA) is used in most wireless receivers are not very efficient since they adopt scheduling technique. The first objective of this paper is to design and verify a low power MC-CDMA receiver and the second objective is to implement the MC-CDMA receiver on FPGA. MC-CDMA act as a processor with the ability to process transmit or receive data simultaneously over a single communication channel. The MC-CDMA design in this paper consists of pipelined FFT and combiner. The primary purpose of pipelined FFT plus combiner module in this research is to execute the instruction on communication (data send and receive) and self-organization. Besides these two modules, there is a memory for temporarily storing the data and an internal clock, among other things. To accomplish these, the designs have been carried out using Verilog coding in Modelsim software, and the design verifications are done through Matlab. The design implementation is via Quartus and on DE2-115 Altera FPGA board. The functionality analyses have been carried out on simulation, and the hardware implementation of the MC-CDMA receiver is tested. Both simulation and hardware execution are successful where the receiver received and displayed the output accordingly. MC-CDMA achieves 39.13mW total power consumption.

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Additional Metadata

Item Type: Article
Divisions: Faculty of Engineering
DOI Number: https://doi.org/10.30534/ijatcse/2019/4781.62019
Publisher: World Academy of Research in Science and Engineering
Keywords: Combiner; FPGA; MC-CDMA; Pipelined FFT; Receiver
Depositing User: Ms. Nida Hidayati Ghazali
Date Deposited: 16 Jun 2021 00:05
Last Modified: 16 Jun 2021 00:05
Altmetrics: http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.30534/ijatcse/2019/4781.62019
URI: http://psasir.upm.edu.my/id/eprint/81250
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