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Design of ultra-low voltage and low-power CMOS current bleeding mixer


Tan, Gim Heng and Mohd Sidek, Roslina and Mohd Isa, Maryam (2014) Design of ultra-low voltage and low-power CMOS current bleeding mixer. In: 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 17-20 Nov. 2014, Ishigaki Island, Okinawa, Japan. (pp. 344-347).


This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4GHz operating frequency band. The proposed mixer uses a modified CMOS current bleeding mixer topology adapting the forward body bias design technique integrated with a NMOS based current bleeding transistor, PMOS based local oscillator (LO) switching stage and on-chip inductors to achieve ultra-low voltage headroom operation down to 0.35V. The conversion gain is further enhanced by integrating an inductor at the gate of the bleeding transistor to reduce RF current leakage. The proposed architecture is simulated and verified in 0.13μm standard CMOS technology. The RC extracted simulation result shows a high conversion gain (CG) of 16dB, 1dB compression point (P1dB) at -17.65dBm, third-order intercept point (IIP3) of -7.45dBm and a noise figure (NF) of 18dB is achieved with a power consumption of 526μW.

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Additional Metadata

Item Type: Conference or Workshop Item (Paper)
Divisions: Faculty of Engineering
DOI Number: https://doi.org/10.1109/APCCAS.2014.7032790
Publisher: IEEE
Keywords: CMOS current bleeding mixer; Ultra-low voltage and low power
Depositing User: Nabilah Mustapa
Date Deposited: 04 Jul 2019 04:13
Last Modified: 04 Jul 2019 04:13
Altmetrics: http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.1109/APCCAS.2014.7032790
URI: http://psasir.upm.edu.my/id/eprint/69373
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