Simple Search:

Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications


Citation

Abdulrazzaq, Bilal Isam and Ibrahim, Omar J. and Kawahito, Shoji and Mohd Sidek, Roslina and Shafie, Suhaidi and Md Yunus, Nurul Amziah and Lee, Lini and Abdul Halin, Izhal (2016) Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications. Sensors, 16 (10). art. no. 1593. pp. 1-15. ISSN 1424-8220

Abstract / Synopsis

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 μm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz.


Download File

[img] PDF
55975.pdf
Restricted to Repository staff only

Download (6MB)

Additional Metadata

Item Type: Article
Divisions: Faculty of Engineering
DOI Number: https://doi.org/10.3390/s16101593
Publisher: MDPI
Keywords: Delay step; Delay range; Time jitter; Delay-locked loop (DLL); Charge pump; Capacitor-reset circuit (CRC)
Depositing User: Nabilah Mustapa
Date Deposited: 03 Jul 2017 09:25
Last Modified: 03 Jul 2017 09:25
Altmetrics: http://www.altmetric.com/details.php?domain=psasir.upm.edu.my&doi=10.3390/s16101593
URI: http://psasir.upm.edu.my/id/eprint/55975
Statistic Details: View Download Statistic

Actions (login required)

View Item View Item