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Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate


Citation

Abdullah, Wan Fazlida Hanim and Mohd Sidek, Roslina and Mohd Saari, Shahrul Aman and Ahmad, Mohd Rais (2002) Electrical performance of 0.5 µm MOSFET on bond-and-etch-back silicon-on-insulator(BESOI) substrate. In: 2nd World Engineering Congress, 22 - 25 July 2002, Sarawak, Malaysia. (pp. 187-192).

Abstract / Synopsis

0.5 µm gate length MOSFET is fabricated on Bond-and-Etch-Back Silicon-On-Insulator (BESOI) substrate using bulk CMOS technology. For the purpose of silicon layer thickness adjustment, sacrificial oxidation is implemented on the device layer of 1.5 ± 0.5 µm device layer and 2 µm buried oxide thickness. Effects of the BESOI substrate and prior sacrificial oxidation on the threshold voltage, drive current and off-state leakage current are investigated from preliminary electrical measurements. Comparison between devices fabricated on bulk silicon and BESOI substrate were carried out. Results are presented in intrinsic transistor performance plots illustrating the relation and variation of critical parameters over the entire wafer.


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Additional Metadata

Item Type: Conference or Workshop Item (Paper)
Divisions: Faculty of Engineering
Keywords: MOSFET; Bond-and-etch-back silicon-on-insulator(BESOI)
Depositing User: Erni Suraya Abdul Aziz
Date Deposited: 26 Feb 2015 12:24
Last Modified: 26 Feb 2015 12:24
URI: http://psasir.upm.edu.my/id/eprint/18493
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