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Development of high speed booth multiplier with optimized stuck-at fault implementation


Citation

Mohammed Khalid, Muhammad Nazir and Wan Hasan, Wan Zuha and Sulaiman, Nasri and Wagiran, Rahman (2002) Development of high speed booth multiplier with optimized stuck-at fault implementation. In: 2nd World Engineering Congress, 22 - 25 July 2002, Sarawak, Malaysia. (pp. 193-198).

Abstract / Synopsis

Multiplier is a basic device in many digital systems such as signal processor, calculator and micro controller. Thus a fast multiplier is very important in improving the speed of the digital system. In general, there are two basic approaches to enhance the speed of the multiplier, Booth Algorithm and the Wallace Tree compressors or counter. Booth Multiplier is proposed due to make sure that multiplication of positive and negative values can be done in 2's complement system operation. For that reason, Booth Multiplier is very demanding to many microprocessor or micro controller chip manufacturers. A part from that, time to market elcaupare very consuming to them, thus failure design can increase production operation and also total costing. So applied DFT is needed due to reduce the production time and total costing. Deterministic technique will be used to detect failure circuit base on test pattern generation. The Test Pattern Generation(TPG) is the process of providing a set of test stimuli plus expected fault free response to meet the requirement of a target fault list. Test for logic circuits are generated to set a sensitive path for a specific fault-effect such Stuck-at-Fault model.


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Additional Metadata

Item Type: Conference or Workshop Item (Paper)
Divisions: Faculty of Engineering
Publisher: Universiti Putra Malaysia Press
Keywords: High speed booth multiplier; Multiplier
Depositing User: Erni Suraya Abdul Aziz
Date Deposited: 26 Feb 2015 16:23
Last Modified: 27 Feb 2015 10:48
URI: http://psasir.upm.edu.my/id/eprint/18396
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