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Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit


Citation

Wan Hasan, Wan Zuha and Ali, Mohd Liakot and Romli, Norfazliana (2002) Optimising built-in-self-test using K-map LFSR on parallel multiplier circuit. In: 2nd World Engineering Congress, 22 - 25 July 2002, Sarawak, Malaysia. (pp. 233-237).

Abstract / Synopsis

Current trend in Integrated Circuits (IC) implementation such as System-on-Chip (SOC) has contributed significant advantages in electronic product features such as high circuit performance with high number of functions, small physical area and high reliability. Therefore, including Built-In-Self-Test (BIST) facility into each subsystem of SOC is considered a good solution. Commonly, BIST structure is based on random test data generation from a Linear Feedback Shift Register (LFSR) due to its simple, small and economical circuit structure. For this reason, development of test pattern" for BIST based on combination of K-map LFSR and deterministic approach could provide one of the solutions to reduce the testing time. This paper describes the test efficiencies based on combination of K-map LFSR features and deterministic test pattern. A parallel multiplier that considered as one of the demanding subsystems is chosen to verify the proposed BIST performance.


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Additional Metadata

Item Type: Conference or Workshop Item (Paper)
Divisions: Faculty of Engineering
Keywords: K-map LFSR; Parallel multiplier circuit
Depositing User: Erni Suraya Abdul Aziz
Date Deposited: 26 Feb 2015 16:17
Last Modified: 26 Feb 2015 16:17
URI: http://psasir.upm.edu.my/id/eprint/18394
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